Conventional approaches for locking a data stream use Phase Lock Loops (PLL) and/or Delay Lock Loops (DLL) to lock or match a clock to an incoming data stream.
Such approaches typically require a very long training sequence and/or a continuous stream of data. Either requirement is incompatible with data communication systems like the Universal Serial Bus (USB), where the data packets can be short and bursty. For USB devices in particular, data may be present for only a very small percentage of the time, which could be less than 1%.
Delay Lock Loops and/or Phase Lock Loops can also suffer from the requirement of (i) long training sequences, (ii) requiring continuous input (e.g., cannot handle bursty data), and/or (iii) may need a precision timing component.